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Preliminary Specifications: Programmed Data Processor Model Three (PDP-3) October, 1960   By:

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PRELIMINARY SPECIFICATIONS

PROGRAMMED DATA PROCESSOR MODEL THREE (PDP 3)

October, 1960

Digital Equipment Corporation Maynard, Massachusetts

TABLE OF CONTENTS

INTRODUCTION 1

General Description 1 System Block Diagram 1 Electrical Description 4 Mechanical Description 4 Environmental Requirements 5

CENTRAL PROCESSOR 6

Operating Speeds 6 Instruction Format 6 Number System 7 Indexing 8 Indirect Addressing 8 Instruction List 9 Manual Controls 20

STORAGE 22

STANDARD INPUT OUTPUT 23

Paper Tape Reader 23 Paper Tape Punch 24 Typewriter 24

OPTIONAL INPUT OUTPUT 26

Sequence Break System 26 High Speed In Out Channel 26 Magnetic Tape 27 CRT Display 33 Real Time Clock 33 Line Printer 34

UTILITY PROGRAMS 35

FRAP System 35 DECAL System 35 Floating Point Subroutines 36 Maintenance Routines 37 Miscellaneous Routines 37

INTRODUCTION

GENERAL DESCRIPTION

The DEC Programmed Data Processor Model Three (PDP 3) is a high performance, large scale digital computer featuring reliability in operation together with economy in initial cost, maintenance and use. This combination is achieved by the use of very fast, reliable, solid state circuits coupled with system design restraint. The simplicity of the system design excludes many marginal or superfluous features and thus their attendant cost and maintenance problems.

The average internal instruction execution rate is about 100,000 operations per second with a peak rate of 200,000 operations per second. This speed, together with its economy and reliability, recommends PDP 3 as an excellent instrument for complex real time control applications and as the center of a modern computing facility.

PDP 3 is a stored program, general purpose digital computer. It is a single address, single instruction machine operating in parallel on 36 bit numbers. It features multiple step indirect addressing and indexing of addresses. The main memory makes 511 registers available as index registers.

The main storage is coincident current magnetic core modules of 4096 words each. The computer has a built in facility to address 8 modules and can be expanded to drive 64 modules. The memory has a cycle time of five microseconds.

SYSTEM BLOCK DIAGRAM

The flow of information between the various registers of PDP 3 is shown in the System Block Diagram (Fig. 1). There are four registers of 36 bit length. Their functions are described below.

Memory Buffer

The Memory Buffer is the central switching register. The word coming from or going to memory is retained in this register. In arithmetic operations it holds the addend, subtrahend, multiplicand, or divisor. The left 6 bits of this register communicate with the Instruction Register. The address portion of the Memory Buffer Register communicates with the Index Adder, the Memory Address Register, and the Program Counter. In certain instructions, the address portion of the control word does not refer to memory but specifies variations of an instruction, thus, the address portion of the Memory Buffer is connected to the Control Element.

Accumulator

The Accumulator is the main register of the Arithmetic Element. Sums and differences are formed in the Accumulator. At the completion of multiplication it holds the high order digits of the product. In division it initially contains the high order digits of the dividend and is left with the remainder... Continue reading book >>




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